1. Field of the Invention
The present invention relates, in general, to SRAM (Static Random Access Memory) devices, and, in particular, certain embodiments of the invention relate to small-sized, high-bandwidth SRAM devices.
2. Description of the Related Art
Cell phones typically have displays, which are generally formed of an LCD or an OLED panel. The image signal of each pixel of the panel is stored in a SRAM device. The SRAM device is a type of memory which doesn't need periodic refresh signals like in a DRAM (Dynamic Random Access Memory) device to hold the stored data. Generally, the SRAM device is composed of an array of SRAM cells.
Referring to FIG. 1, a schematic circuit diagram of a traditional SRAM cell is shown. Unlike a DRAM device which stores data in a capacitor, data held in a SRAM cell are stored in a pair of cross-coupled inverters which consist of NMOS (N-Channel Metal Oxide Semiconductor) transistors 11, 12 and PMOS (P-Channel Metal Oxide Semiconductor) transistors 13, 14, known as a Flip-Flop. For a six-transistor SRAM cell, the drain electrode of NMOS transistor 11 is connected to the drain electrode of PMOS transistor 13 and the drain electrode of NMOS transistor 12 is connected to the drain electrode of PMOS transistor 14. The gate electrode of NMOS transistor 11 is connected to the gate electrode of PMOS transistor 13 and the drain electrode of NMOS transistor 12. The gate electrode of NMOS transistor 12 is connected to the gate electrode of PMOS transistor 14 and the drain electrode of NMOS transistor 11. In addition, the drain electrode of the NMOS transistor 11 is also connected to the source electrode of a first access transistor 15, and the drain of the NMOS transistor 12 is connected to the source electrode of a second access transistor 16. Furthermore, the drain electrode of the first access transistor 15 is connected to one of the bit lines 20, and the drain electrode of the second access transistor 16 is connected to one of the n-bit lines 22. Moreover, the gate electrodes of the first access transistor 15 and the second access transistor 16 are connected to one of the word lines 24. The source electrodes of PMOS transistor 13 and PMOS transistor 14 are further connected to the power source VDD, and the source electrodes of the NMOS transistor 11 and NMOS transistor 12 are grounded.
Referring now to FIG. 2, a schematic electric diagram of a traditional SRAM cell array is shown. The SRAM cell array shown in FIG. 2 is an (M+1)×(N+1) array, having (M+1) rows and (N+1) columns of SRAM cells. The SRAM cells on the zeroth row of the SRAM cells array (the lowest one in FIG. 2) are connected to the zeroth word line (the lowest one in FIG. 2, shown as “WL0”). The SRAM cells on the first row of the array are connected to the first word line, shown as “WL1” in FIG. 2, and those on the M-th row of the array (the highest one in FIG. 2) are connected to the M-th word line, shown as “WLM”. On the other hand, the SRAM cells on the zeroth column of the SRAM cells array (the leftmost one in FIG. 2) are connected to the zeroth bit line and zeroth n-bit line (the leftmost one in FIG. 2, shown as “BL0” and “n-BL0”). The SRAM cells on the N-th column of the SRAM cells array (the rightmost one in FIG. 2) are connected to the N-th bit line and N-th n-bit line (the rightmost one in FIG. 2, shown as “BLN” and “n-BLN”).
Each SRAM cell in the array is connected to a specific word line and a specific bit line and n-bit line. Each word line is coupled to a X-decoder which will be illustrated in FIG. 3 below. Similarly, each bit line and each n-bit line will be coupled to a specific Y-decoder, as shown in FIG. 3 below.
Referring now to FIG. 3, a schematic diagram of a traditional SRAM device is shown. The SRAM device includes a SRAM cell array 30, which is connected to one X-decoder 32, a first Y-decoder 34, and a second Y-decoder 36. The X-decoder 32 is a word line decoder, which is used to access the desired address word line. The first Y-decoder 34 and the second Y-decoder 36 are utilized to access the desired address bit line. Matching a specific word line and a specific bit line can enable a specific SRAM cell in the array. Both the X-decoder 32 and the first Y-decoder 34 are driven by a micro-controller 37, such as a CPU or an ASIC.
The first Y-decoder 34 is connected to a first sense amplifier 38, and the second Y-decoder 36 is connected to a second sense amplifier 39. The first sense amplifier 38 and the second sense amplifier 39 are used to retrieve data from the SRAM cell array, by receiving differential complimentary signals on the bit lines and the n-bit lines and reading the data (logic high “1” or logic low “0”) stored in each specific SRAM cell. Further, the second sense amplifier 39 is further connected to a line buffer 41 and then coupled to a LCD source or other target.
To prolong the work and standby duration of the cell phone, it is desirable to use a low power consumption SOC driver. However, the SRAM device used to store the image signal of each pixel consumes a large amount of power. For this reason, it is desirable to reduce the power consumption for a portable SOC driver both in the operational and standby stages. The lower the power consumption of the SRAM device, the longer the operational and standby durations can be.
Furthermore, the required physical size of the SRAM device is another important issue. By reducing the physical size of the SRAM device, lower manufacturing costs of the SRAM device may be obtained.
Accordingly, there is a need for an improved design for SRAM devices, to achieve reduced physical size SRAM devices and increase the work or standby duration.